Ordinary syntax and semantics for VerilogR HDL-based RTL synthesis are defined during this ordinary.
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Additional info for 1364.1-2002 IEEE Standard for Verilog Register Transfer Level Synthesis
Furthermore, event control shall appear only in the top-level statement (the statement with the always keyword) as described in Clause 5. Event control shall not be allowed in inner statements. 4 Event or operator Supported. 5 Implicit event_expression list Supported. 7 Intra-assignment timing controls blocking_assignment ::= variable_lvalue = [ delay_or_event_control ] expression nonblocking_assignment ::= variable_lvalue <= [ delay_or_event_control ] expression 50 Copyright © 2002 IEEE. All rights reserved.
2 The drive strength speciﬁcation Ignored. 3 The delay speciﬁcation Ignored. 4 The primitive instance identiﬁer Supported. 5 The range speciﬁcation Supported. 6 Primitive instance connection list Supported. 2 and, nand, nor, or, xor, and xnor gates Supported. 3 buf and not gates Supported. 4 buif1, buﬁf0, notif1, and notif0 gates Supported. 44 Copyright © 2002 IEEE. All rights reserved. 5 MOS switches Not supported. 6 Bidirectional pass switches Not supported. 7 CMOS switches Not supported. 8 pullup and pulldown sources Not supported.
3 Trireg net Not supported. 4 Tri0 and tri1 nets Not supported. 5 Supply nets Supported. 36 Copyright © 2002 IEEE. All rights reserved. 6 regs Supported. See Clause 5 on how edge-sensitive and level-sensitive storage devices are inferred. 1 Operators and real numbers Not supported. 2 Conversion Not supported. 9 Arrays Supported. 1 Net arrays Supported. 2 reg and variable arrays Supported. 3 Memories Supported. Copyright © 2002 IEEE. All rights reserved. 2 Local parameters—localparam Supported. 11 Name spaces Supported.
1364.1-2002 IEEE Standard for Verilog Register Transfer Level Synthesis